Allen Baum, Chair of the RISC-V International Architecture Test SIG
Esperanto Technologies, Inc.
The RISC-V open standard ISA offers a compatibility framework, yet has built-in flexibility across the specification envelope.
The Imperas contribution of new Crypto extension tests is a welcome addition to the trusted test suite portfolio, supporting implementers with verification of their hardware.
Jingliang (Leo) Wang, Co-chair of the OpenHW Group Verification Task Group
Futurewei Technologies
The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores. The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution.
The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.