The design freedoms of RISC-V and vector extensions are changing the traditional boundaries between the software and hardware phases of SoC development.
The Imperas models of the SiFive cores help developers with SoC architectural exploration across the full flexibility of the SiFive Core IP Portfolio, and support early software development, which is a critical factor in validating new AI solutions.
Itai Yarom, VP of Sales and Marketing
MIPS, Inc.
As a developer of leading high-performance RISC-V application processors, verification standards are an important companion to the RISC-V specifications.
Verification standards such as RVVI provide a solid foundation that supports all RISC-V adopters, from basic embedded cores through to complex application processors with multi-cluster, multi-core, multi-threading and out-of-order pipelines.