Imperas release of Imagination Technologies MIPS Warrior IP core models - Embedded Computing Design - Rich Nass
Comments on Imperas Software, Green Hills Software announcments about how their support with models and tools boost Imagaination's MIPS architecture and move its ecosystem forward.
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Comments
Gerard Rauwerda, CTO
Recore SystemsImperas allowed us to quickly add our own components and build the topologies which we wanted to test. We had our first demo up and running in 20 minutes, and it took us just a few days to build a reference hardware architecture based on components in the Extendable Platform Kit (EPK). Last but not least, after just a few months we could start playing with our own many-core operating system on our many-core hardware design. The ease of use of the EPK, together with excellent Imperas documentation and support, have kick-started our FlexaWare platform development.
Steve Richmond, Co-chair of the OpenHW Group Verification Task Group
Silicon LaboratoriesSimulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog.
The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.