Bill McSpadden, Principal VLSI Verification Engineer
Seagate Technology
The Imperas Golden RISC-V Reference Model helped us find many bugs in our cores.
However, the RISC-V architectural tests yielded no bugs, which is expected since the architectural tests are a subset of full verification.
David Kelf, CEO
Breker Verification Systems
RISC-V represents an inflection point for semiconductor verification as the design freedoms provided by the open ISA means an assumption of the responsibility of the processor and system verification task.
In partnering with Imperas, the leaders in RISC-V processor verification, we can offer a combination of technologies and interface standards for IP and SoC testing that ensures commercial grade verification for these flexible devices right through to the end platform.