By integrating our Xcelium Logic Simulator with Imperas's RISC-V verification technology, we've empowered NSITEXE to design the next-generation of its Akaria processors, which are optimized for safety-critical applications and compliant with the ISO 26262 ASIL D standard.
Our work together exemplifies Cadence’s commitment to collaboration and innovation to support our customers in the rapidly evolving semiconductor industry.
Dr. Charlie Su, President and CTO
Andes Technology Corp.
RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations.
The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.