New design innovations with RISC-V offer great potential in automotive applications, but achieving the extensive quality standards are critical for success.
The verification requirements to achieve the ASIL D safety requirement level of ISO 26262 with a processor-based design are extensive, however verification IP reuse through standards such as RVVI help improve efficiency and achieve time to market schedules with all the design innovations that RISC-V enables.
Kazutoshi Wakabayashi, Senior Manager
Embedded Systems Solution Division, NEC
OVP is widely used by our customers, who demanded the integration with CyberWorkBench. This integration significantly broadens CWB's HW/SW co-verification support. We were also very impressed with Imperas technical support helping us achieve this integration extremely quickly and efficiently.