Michal Siwinski, Group Director, System Realization
Cadence Design Systems
High performance processor models are an important part of our virtual prototype solution. The Open Virtual Platforms library of fast processor core models, together with Imperas tools for software analysis, complement the Virtual System Platform to provide an effective solution for system and software development.
Jingliang (Leo) Wang, Co-chair of the OpenHW Group Verification Task Group
Futurewei Technologies
The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores. The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution.
The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.