Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project
ETH Zurich
RISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.
Shubhodeep Roy Choudhury, Managing Director & Co-founder
Valtrix Systems
As the leading provider of commercial RISC-V Instruction Stream Generators, it is essential for verification standards for test benches and verification IP reuse to evolve.
Adopting RVVI virtual peripherals provides additional flexibility and efficiency for our flagship verification product STING to target asynchronous event verification, which is essential for quality RISC-V processor functional design verification