Steve Richmond, Co-chair of the OpenHW Group Verification Task Group
Silicon Laboratories
Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog.
The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.
Krishna Raghavan, President
MIPS IP Licensing, Wave Computing
The Imperas simulation and modeling technology has been a reliable and high-quality testing model used internally by the MIPS engineering team for many years. We are delighted to partner with Imperas to make this industrial-grade simulation technology available to support the MIPS Open program and further the momentum around open hardware development.