Shubhodeep Roy Choudhury, Managing Director & Co-founder
Valtrix Systems
As the leading provider of commercial RISC-V Instruction Stream Generators, it is essential for verification standards for test benches and verification IP reuse to evolve.
Adopting RVVI virtual peripherals provides additional flexibility and efficiency for our flagship verification product STING to target asynchronous event verification, which is essential for quality RISC-V processor functional design verification
Hiroyasu Hasegawa, CTO
hd Lab, Japan
For our SystemC training courses, we want the attendees to focus on building SystemC models, and how to use those models. By using OVP Fast Processor Models, which work easily in SystemC virtual platforms, students do not have to worry about processor models, and are able to get the most out of our courses. The OVP models work well in our SystemC environment and also with other SystemC tools. We are excited to be able to expand our design service offerings in virtual platforms to our customers.