Comments
Rick O’Connor, President & CEO
OpenHW GroupThe open RISC-V ISA specification is an excellent starting point and open-source processor IP cores, such as the CORE-V family, have real potential to change the industry.
The high-quality open-source CORE-V CV32E40P core now allows the broadest participation in the RISC-V revolution, the OpenHW MCU Dev/Kit project is just one example of the innovations that can now be developed from the quality foundation provided by the CV32E40P core, having been verified with the CORE-V-VERIF testbench which leverages the Imperas RISC-V golden reference model.
Gerard Rauwerda, CTO
Recore SystemsImperas allowed us to quickly add our own components and build the topologies which we wanted to test. We had our first demo up and running in 20 minutes, and it took us just a few days to build a reference hardware architecture based on components in the Extendable Platform Kit (EPK). Last but not least, after just a few months we could start playing with our own many-core operating system on our many-core hardware design. The ease of use of the EPK, together with excellent Imperas documentation and support, have kick-started our FlexaWare platform development.