Chuanhua Chang, Chair of RISC-V International P Extension Task Group
Andes Technology Corp.
Flexibility within a framework of compatibility is the essential foundation of the RISC-V ISA.
The RISC-V P extension defines a rich set of integer SIMD/DSP instructions operating on existing integer registers to support complex data processing within the constraints of real-time applications. However, the hardware specification is just the start - adoption and success depend on the software ecosystem, which is supported with the reference models and test suites from Imperas.
Jérôme Quévremont, vice-chair of OpenHW Cores Task Group
Thales Research & Technology
Following the success of the CV32E40P verification, riscvOVPsimCOREV was selected as a reference model for the CVA6 application cores.
The selection by Imperas of a freeware license model to support CORE-V IPs is a great move towards the adoption of OpenHW industrial-grade CORE-V processor cores by a broader community.