RISC-V represents an inflection point for semiconductor verification as the design freedoms provided by the open ISA means an assumption of the responsibility of the processor and system verification task.
In partnering with Imperas, the leaders in RISC-V processor verification, we can offer a combination of technologies and interface standards for IP and SoC testing that ensures commercial grade verification for these flexible devices right through to the end platform.
Krishna Raghavan, President
MIPS IP Licensing, Wave Computing
The Imperas simulation and modeling technology has been a reliable and high-quality testing model used internally by the MIPS engineering team for many years. We are delighted to partner with Imperas to make this industrial-grade simulation technology available to support the MIPS Open program and further the momentum around open hardware development.