Comments
Dr. Charlie Su, CTO and EVP
Andes TechnologyAll Andes RISC-V CPU cores are extensible. ACE empowers SoC designers to easily add custom instructions on top of our highly efficient cores to fulfill domain-specific acceleration and bring their SoC performance to the next level.
Our RISC-V CPU cores are supported by the Imperas simulators already. We are excited to extend our cooperation to enable ACE users to use the Imperas fast simulators so that software engineers can also be engaged with the full development cycle and from the early stage.
Stephan Werner
Karlsruhe Institute of TechnologyM*SDK, the OVP APIs and the OVP library of models have been a great asset to the FlexTiles project, enabling us to quickly create a virtual platform for our advanced architecture. We were able to use the Imperas technology and tools to develop multiple demonstrations of the FlexTiles architecture, including multiple hardware configurations, the Network on Chip (NoC) developed in this project and the operating system and software tools for FlexTiles.