Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project
ETH Zurich
RISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.
Chris Jones, VP product marketing
SiFive, Inc.
The design freedoms of RISC-V and vector extensions are changing the traditional boundaries between the software and hardware phases of SoC development.
The Imperas models of the SiFive cores help developers with SoC architectural exploration across the full flexibility of the SiFive Core IP Portfolio, and support early software development, which is a critical factor in validating new AI solutions.