The design freedoms of RISC-V and vector extensions are changing the traditional boundaries between the software and hardware phases of SoC development.
The Imperas models of the SiFive cores help developers with SoC architectural exploration across the full flexibility of the SiFive Core IP Portfolio, and support early software development, which is a critical factor in validating new AI solutions.
Guy Rabbat, President and CEO
Ashling Systems Corporation
Our integration with Imperas brings Ashling closer to our vision to become the provider of a complete RISC-V turnkey solution.