All Andes RISC-V CPU cores are extensible. ACE empowers SoC designers to easily add custom instructions on top of our highly efficient cores to fulfill domain-specific acceleration and bring their SoC performance to the next level.
Our RISC-V CPU cores are supported by the Imperas simulators already. We are excited to extend our cooperation to enable ACE users to use the Imperas fast simulators so that software engineers can also be engaged with the full development cycle and from the early stage.
Allen Baum, Chair of the RISC-V International Architecture Test SIG
Esperanto Technologies, Inc.
The RISC-V open standard ISA offers a compatibility framework, yet has built-in flexibility across the specification envelope.
The Imperas contribution of new Crypto extension tests is a welcome addition to the trusted test suite portfolio, supporting implementers with verification of their hardware.