Comments
Rick O’Connor, President & CEO
OpenHW GroupThe OpenHW Verification Task Group contributors are pioneers in the drive to advance the quality of open-source hardware IP ready for mainstream adoption – quality deliverables are the hallmark of any trusted IP provider, commercial or open source.
OpenHW membership growth over the past three years is expanding the roadmap of IP core projects dramatically, with projects addressing the needs for application class devices supporting Linux, embedded security, and compute intensive applications with custom instructions. The RVVI open standard and flexible methodology significantly helps the OpenHW Verification Task Group members and contributors with efficient and quality verification for the full range of CORE-V IP projects.
Chuanhua Chang, Chair of RISC-V International P Extension Task Group
Andes Technology Corp.Flexibility within a framework of compatibility is the essential foundation of the RISC-V ISA.
The RISC-V P extension defines a rich set of integer SIMD/DSP instructions operating on existing integer registers to support complex data processing within the constraints of real-time applications. However, the hardware specification is just the start - adoption and success depend on the software ecosystem, which is supported with the reference models and test suites from Imperas.