Allen Baum, Chair of the RISC-V International Architecture Test SIG
Esperanto Technologies, Inc.
Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture.
The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.
Rick O’Connor, President & CEO
OpenHW Group
One aspect that all RISC-V processor designers agreed on, both commercial vendors and open-source developers, is that quality is the key to successful IP core adoption.
The OpenHW Group have supported the adoption of RVVI from its inception through the member contributors in the OpenHW Verification Task Group, and now welcome the new features and growing adoption by the commercial community.