Associate Professor, Northeastern University, Boston, USA
I find Imperas tools and models invaluable for my research and my course, High Level Design of Hardware Software Systems. My students can now explore and command state-of-the-art prototyping technology for complex systems.
Richard Newell, Associate Technical Fellow
Microchip
The new scalar cryptography extension for RISC-V is designed to be lightweight and to be suitable for 32- and 64-bit base architectures, from embedded, IoT class cores to large, application class cores.
The working group coordinates the member driven contributions and we welcome the Imperas Crypto tests to support the early implementors and adopters.