Shubhodeep Roy Choudhury, Managing Director & Co-founder
Valtrix Systems
As the leading provider of commercial RISC-V Instruction Stream Generators, it is essential for verification standards for test benches and verification IP reuse to evolve.
Adopting RVVI virtual peripherals provides additional flexibility and efficiency for our flagship verification product STING to target asynchronous event verification, which is essential for quality RISC-V processor functional design verification
Arjan Bink, chair of OpenHW Cores Task Group
Silicon Laboratories
High quality IP is an important deliverable that others can build on, but developers need more than just processor RTL to support high quality implementations.
All embedded software is closely related to the IP core it will run on; thus, an accurate ISS reference model is essential for all HW and SW adopters. riscvOVPsimCOREV is the key starting point for the support of the OpenHW CORE-V cores by the ecosystem.