x

Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

MIPS core models and QuantumLeap Parallel Simulation using multi-core host PC gaining significant simulation speed.

A demonstration video showing the MIPS core models and Imperas QuantumLeap accelerator on several examples on a 4 core i7-3770 host PC to gain up to 22 billion Instructions a second.The video show gains on an SMP platform that incorporates a proAptiv 4 processor core and shows it running 4 applications in parallel and shows the QuantumLeap performance increase.The video concludes showing AMP peak performance of over 22 billion instructions per second on a 4 processor proAptiv core:

Comments

  • Philippe Luc, Verification Director

    Codasip

    Imperas are the pioneers in simulation technology and processor verification for RISC-V.

    While processor verification is not a new problem, there are many RISC-V suppliers, with customization and various levels of verification or conformance: customers are legitimately concerned about both quality and fragmentation. Codasip is very proud of our rigorous approach to verification– using Imperas as an important part of our quality process furthers extend our differentiation. The Imperas independence, reputation and technical strength provides our customers with further reassurance in our ‘best in class’ RISC-V processors.

  • Alexander Redkin, CEO

    Syntacore

    As one of the first IP providers for RISC-V cores, we see the importance of compliance as the RISC-V ecosystem develops. riscvOVPsim is a solid starting point for developers looking for a RISC V ISS (Instruction Set Simulator) for test and verification.