All Imperas News

Design Automation Conference, June 2-6, Austin, Texas

If you are heading to the Design Automation Conference (DAC) in Austin, Texas, taking place June 2-6, Larry Lapides will be attending.  He would enjoy learning more about your virtual platform and software development requirements, as well as discussing the second generation Imperas products, including the Developer range of products and M*SDK.  Please contact sales@imperas.com to set up a meeting at DAC.

Visit us at the Multicore Developers Conference, May 21-22, Santa Clara, California

The Multicore Developers Conference (MDC) is focused on the discussion of both technical and business issues of designing and using multicore processors.   

Imperas at MDC:  Larry Lapides is presenting a paper, and Imperas will have a booth in the exhibits where we will be demonstrating solutions for software verification, analysis and profiling, ranging from code coverage and profiling to OS context switching analysis and fault injection.  Exhibit hours are Tuesday 12:30 – 2:30pm and 4:30 – 6:30pm, and Wednesday 12:15 – 2:15pm. 

Virtual Platform Based Software Debug & Testing for Multiprocessor/Multicore Systems, Larry Lapides, Wednesday May 22, 3:45pm

Abstract: 
As electronics systems get more complex, quality becomes a much bigger issue.  Solving the quality issue means improved debug and testing tools and methodologies.  Virtual platforms (software simulation) provide one approach, not only for functional software testing but also adding more advanced test and analysis capabilities like code coverage, profiling, fault injection and more.  Moreover, these tools can be implemented in a completely non-intrusive manner, adding validity to the testing methodology. 

Imperas Delivers ARM Cortex-A7 MPCore High-Performance Processor Model with Integrated Software Development Environment

Company’s Range of ARM Cortex Models, Including Cortex-A15 with TrustZone® and Virtualization, will be Demonstrated at the Multicore Developers Conference in May 2013

OXFORD, United Kingdom, April 9th, 2013 - Imperas has today released its latest software model, the ARM Cortex-A7 MPCore, to complement its existing range of ARM Cortex models.

The model uses Imperas high performance code morphing technology to allow software engineers to execute development code at hundreds of million of instructions per second. Incorporated within the model is Imperas range of advanced development tools for efficient software analysis and debug.

“The ARM Cortex processors include capabilities, such as TrustZone and Virtualization, that must be modeled accurately to ensure absolutely reliable software execution during the verification process,” highlighted Simon Davidmann, CEO of Imperas. “Our library is unusual in that it includes fully featured models, which operate at the highest available performance, and include a powerful software development environment.”

ARM Cortex-A15 and Cortex-R4 Fast Processor Models Provided by Imperas and OVP

Open Source Models Available From Open Virtual Platforms

OXFORD, United Kingdom, October 25, 2012 - Imperas, which is a member of the ARM Connected Community, has released its models of the ARM Cortex-A15, Cortex-R4, Cortex-R4F and ARM1176 processor cores. These models, as with all OVP models of the ARM processor cores, are now available from Open Virtual Platforms (OVP). Support from OVP includes example virtual platforms incorporating the cores, with the processor core models also supported in Imperas' advanced software development tools. The models, together with the OVP and Imperas M*SDK tools, will be demonstrated at the ARM TechCon conference October 31 and November 1 in Santa Clara.

The OVP Fast Processor Models and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/ARM. The new models of the ARM processor cores, as well as models of the other ARM processors including the ARM7, ARM9, ARM10, ARM11 and Cortex-A, Cortex-R, and Cortex-M families, work with the Imperas and OVP simulators, and have shown exceptionally fast simulation performance of hundreds of millions of instructions per second. The OVP Fast Processor Models include support for both the 32 and 16-bit instructions, as well as the MMU, MPU, TCM, VFP, NEON, TrustZone, virtualization and Large Physical Address Extension (LPAE) features.

Yikes! CoWare, VaST, Virtutech acquired in a week - changes in virtual platform space - Cooley Blog

An interesting contributed blog on the changes in the virtual platform space by John Cooley of ESNUG and DeepChip

John Cooley, though focused on the EDA simulation, synthesis, and RTL areas collected some information regarding the recent acquisitions.

There are contributions from:

  • Jay Vleeschhouwer of Ticonderoga Securities
  • Simon Davidmann of Imperas
  • Bill Neifert of Carbon
  • Brett Cline of Forte Design
  • and several annonymous contributors

To read the full article, please visit the blog on deepchip.com here

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