All Imperas News

New models for MIPS Warrior CPUs

With the run up to the Embedded World conference and exhibition in Germany in February, Larry Lapides of Imperas contributed a guest blog for Imagination on the latest OVP Fast Processor models for the new MIPS Warrior range.

The blog talks about several items related to Imperas, OVP and Imagination's MIPS models. It also provides the outline for the Embedded World paper on accelerating simulation using multi-core host PCs and also provides links to other related topics.

To read the blog, please visit the Imagination Blog Site.

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Extendable Platform Kits for MIPS Released by Imperas

Enabling quick start for developing and testing software

Oxford, United Kingdom, 20 November 2014 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, announced the availability of Extendable Platform Kits™ (EPKs™) for MIPS CPU cores from Imagination Technologies.

These EPKs for MIPS, available for download from the Open Virtual Platforms™ (OVP™) website, are designed to provide a base for users to run high-speed simulations of MIPS-based SoCs and platforms on any suitable PC. They are based on the functionality of Imagination’s MIPS FPGA evaluation platforms, enabling anyone to simulate MIPS-based systems using Imagination’s reference platforms. EPKs provide a base for users to extend the functionality of the virtual platform, to closer reflect their own platform, by adding more component models, running different operating systems or adding additional applications.

Kyma Systems Selects Imperas Virtual Platform Tools for Hypervisor Development

Imperas M*SDK used for KVM development supporting MIPS hardware virtualization instructions

Oxford, United Kingdom, June 3rd, 2014 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, announced today that Kyma Systems has been successfully using the Imperas M*SDK™ for virtual platform-based development of hypervisors.  M*SDK enabled porting of the KVM hypervisor to support Imagination Technologies' latest MIPS cores with virtualization extensions.  The OS- and CPU-aware tools included with M*SDK also enabled more comprehensive and faster testing of the hypervisor.     

Imperas Exhibiting at the Design Automation Conference, June 2-6, 2014 in San Francisco

Imperas is exhibiting at the Design Automation Conference, June 2-6 in San Francisco.  We will be in the ARM Connected Community Pavilion in the Exhibit Hall.  Come by to see our demos of the ARMv8 ISS, and Extendable Platform Kits (EPKs) booting Linaro Linux, both providing the fastest simulation of ARMv8 processors. 

At DAC, Simon Davidmann, Imperas CEO, is on a panel on Tuesday morning, titled “Open Source Embedded Software: Savior or Slayer?”, and is presenting a paper titled “Simulation Based Analysis and Debug of Heterogeneous Platforms” in the session on Heterogeneous Computing Platforms on Wednesday afternoon.

Imperas Announces ARMv8 ISS and ARMv8 Platform Roadmap

Imperas ISS is fastest ARMv8 simulation available

Oxford, United Kingdom, May 6th, 2014 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation and processor core models, has released an Instruction Set Simulator (ISS) for the ARMv8-A architecture.  In addition, Imperas announced its roadmap for products and virtual platforms supporting the ARMv8 family, including having two Extendable Platform Kits™ (EPKs™) available by the end of Q2. 

The ARMv8-A architecture currently has two core families, Cortex™-A53 and Cortex-A57.  The ARMv8-A architecture is ARM’s first 64-bit processor architecture, with initial licensees being primarily in the mobile and server market segments.  With a new architecture, new cores and, in the server space, new applications for ARM® cores, testing of the software becomes increasingly important.  With test suites typically consisting of hundreds or even thousands of tests, each of over 10 billion instructions, simulation speed is critical for robust and comprehensive testing of the software.

The Imperas simulation solutions together with the Imperas ARMv8 ISS and upcoming Imperas ARMv8 processor models provide the highest simulation performance available in the market.

Imperas Presents at TVS 2014 Virtual Platform Software Simulation for Enhanced Multi-core Software Verification

Imperas CEO, Simon Davidmann presented a paper at the TVS Software Testing Conference in March 2014. This presentation discussed the use of Virtual Platforms for embedded software development, discusses how high performance simulation can find bugs quicker, and demonstrates the Imperas parallel simulation technology QuantumLeap. Imperas tools are also discussed and a case study of using them to find bugs in OS porting is presented.

To see the presentation visit here on the Imperas website, to watch the video click here.

 

CDNLive, 11-12 March 2014, Santa Clara, California. Imperas Presenting a paper on the importance of simulation speed for software quality

CDNLive is March 11-12 in Santa Clara, California and is organized by Cadence Design Systems.  Imperas will be presenting a paper titled “Software Quality is Directly Proportional to Simulation Speed” as part of Track 6, at 4pm Tuesday March 11th.  Here is the abstract: 

“Software quality is directly proportional to simulation speed.”  This is obvious, even intuitive, for engineers.  Faster simulations mean more tests can be run, which in turn means more bugs can be found, which results in higher quality.  Reduced schedules can be a side benefit of speed. 

While this is obvious, why is it so important right now?  One example is server SoCs, where software/systems test suites can include hundreds of tests, each consisting of hundreds of billions of instructions.  If the virtual platform performance is 100 MIPS, this test suite could take over one week to run.  If the performance is five times faster, running the test suite takes 1 day; ten times faster and it runs overnight.  This simulation speed is especially interesting with the new generation of ARMv8 based server SoCs.  It is also interesting in areas such as image recognition, where hardware accelerators sit next to the CPUs on the SoC. 

DVCon, 3-6 March 2014, San Jose, California. Imperas present paper

DVCon is March 3-6 in San Jose, California.  Imperas will be presenting a paper titled “Learning From Advanced Hardware Verification for Hardware Dependent Software” as part of Session 3, at 9:30am Tuesday March 4th.  Here is the abstract: 

We present a new perspective for embedded software verification for generalized multicore processor platforms, somewhat analogous to simulation-centric hardware verification solutions. A spatial, temporal, and abstract multi-dimensional framework for software verification, profiling, analysis, and debug is proposed that leverages a specialized simulation core. The simulator enables key services for the verification solution while providing a degree of separation from both the hardware models and software under test, to ensure accurate behavioral representation, as well as customization and performance advantages.

This paper will discuss requirements for modern embedded software development and solutions utilized to date, before discussing this simulation-based solution and the dimensional framework layered above. We will also discuss two real life scenarios where the solution is utilized to affect.

Embedded World, 25-27 Feb 2014, Nuremberg, Germany. Imperas present paper, demos in partner booths

Embedded World is February 25-27 in Nuremberg, Germany.  Imperas will be presenting a paper titled “Customized, Intelligent Memory Access Monitoring for Reliable Asymmetric MultiProcessor System Development” in Session 23, Thursday at 14:00.  We will be available for demos of the Imperas simulation and software development, debug and test tools in the Altera booth Tuesday and Wednesday from 10:00-11:00 and 14:00-15:00, and Thursday from 10:00-11:00.  We will also be in the Imagination Technologies booth for demos of the Imperas tools for MIPS cores.

Here is a brief summary of the paper: 

The use of Asymmetric MultiProcessor (AMP) architectures is now widespread.  Two common implementations are Linux running on one core of a dual-core ARM Cortex-A9, with an RTOS running on the other, and SMP Linux running on the dual-core ARM Cortex-A9 and an RTOS or bare metal application running on another processor core, such as an Altera NIOS II. The reliability of such a system is highly dependent on the correct functioning of inter-core interaction with shared resources, which is often hard to verify. 

Imperas Supports Imagination MIPS Cores With Fastest Ever Processor Model Simulation

QuantumLeap parallel simulation accelerator enables virtual platform performance of greater than 16 billion instructions per second, the fastest commercial solution available today

Oxford, United Kingdom, February 4th, 2014 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, has added support for models of Imagination Technologies’ MIPS processors to QuantumLeap™, a parallel simulation performance accelerator.

QuantumLeap leverages Imperas’ new synchronization algorithm to provide the fastest virtual platform software execution speed available today on standard, multi-core Personal Computer (PC) host machines.  The Imperas technology - simulation plus processor core models - provides the MIPS ecosystem with the fastest software simulation solution in the industry. 

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