All Imperas News

Imperas Supports Imagination MIPS Cores With Fastest Ever Processor Model Simulation

QuantumLeap parallel simulation accelerator enables virtual platform performance of greater than 16 billion instructions per second, the fastest commercial solution available today

Oxford, United Kingdom, February 4th, 2014 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, has added support for models of Imagination Technologies’ MIPS processors to QuantumLeap™, a parallel simulation performance accelerator.

QuantumLeap leverages Imperas’ new synchronization algorithm to provide the fastest virtual platform software execution speed available today on standard, multi-core Personal Computer (PC) host machines.  The Imperas technology - simulation plus processor core models - provides the MIPS ecosystem with the fastest software simulation solution in the industry. 

Imperas Delivers QuantumLeap Simulation Synchronization – Industry's First Parallel Virtual Platform Simulator

Parallel synchronization technology augments existing high-performance simulator to accelerate virtual platforms beyond 16,000 MIPS, the fastest commercial solution available today

Oxford, United Kingdom, October 22nd, 2013—Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, has released QuantumLeap™, a parallel simulation performance accelerator. QuantumLeap leverages a new synchronization algorithm to provide the fastest virtual platform software execution speed available today on standard, multi-core Personal Computer (PC) host machines.

The execution performance of this new technology has been measured on average at 15 times faster than the nearest commercial solution using standard benchmarks.

Many current System-on-Chip (SoC) hardware platforms, for example mobile and server devices, incorporate multi-core embedded processors coupled with hardware accelerators, all executing in parallel. The performance of existing, single-threaded virtual platform simulators does not adequately scale for these SoCs, creating a barrier to efficient virtual platform-based software development.

Altera Nios II Processor Model Delivered By Imperas

Open source simulation model enables Altera customers to more easily validate and debug Nios II embedded software

San Jose, Calif., October 22nd, 2013—Imperas Software Ltd. (www.imperas.com), founder of the Open Virtual Platforms™ (OVP™) consortium, today announced the availability of the Altera Nios II embedded processor OVP model. Jointly developed by Imperas and Altera, this open source model will enable a high-performance development environment for Nios II embedded software.

The OVP Fast Processor Model of the Nios II may be configured at start-up to match the intended behavior of the actual FPGA component, but will execute significantly faster than real-time. This allows embedded software to be tested more rigorously and earlier in the design process, accelerating complex software development cycles.

“Imperas led formation of the Open Virtual Platforms consortium to improve the embedded software development experience,” said Simon Davidmann, CEO of Imperas. “With Altera, we have taken an important step today by providing designers with a high-performance model of the Altera Nios II processor, executing many times faster than other development offerings to enable the most comprehensive software verification solution available.”

Imperas™ Provides Comprehensive ARM® TrustZone® Modeling Kit For OVP-Based Virtual Platforms

Kit Includes Modeling Application Note and Four Open Source, Executable Platform Examples Based Upon OVP™ ARM Cortex™ Processor Models With TrustZone Technology

OXFORD, United Kingdom, October 8th, 2013 – Imperas Software Ltd. (www.Imperas.com), a pioneer of advanced embedded software development systems using virtual platforms, today made available a System Modeling Kit designed to simplify the creation of high-performance virtual platforms that incorporate the ARM TrustZone technology.

The System Modeling Kit provides four open source virtual platform reference models, together with an application note and video, to demonstrate best modeling practices for systems based on TrustZone. The kit is designed to accelerate the learning curve for modeling TrustZone-based hardware, to provide high-performance, accurate virtual platforms that accelerate system verification, and make available immediate solutions for the execution of software stacks that incorporate security solutions based on TrustZone.

Imperas™ Releases the PowerPC® 4xx Range of High-Performance Processor Models with Integrated Software Development Environment

Open Virtual Platforms (OVP™) Fast Processor Model Supports the PowerPC 440™, PowerPC 460™, PowerPC 470™ and PowerPC 476™ Variants of the Popular Processor

OXFORD, United Kingdom, September 26, 2013 – Imperas Software, Ltd. has today released its latest OVP Fast Processor Model for the POWER.org architecture. The new Imperas model of the IBM PowerPC 4xx range supports the PowerPC 440, PowerPC 460, PowerPC 470 and PowerPC 476 variants. The model is available as part of the OVP library, allowing for free access to OVP users.

The IBM PowerPC 4xx processor range is widely utilized by many companies today in a range of applications including automotive, compute servers, military and aerospace, wired and wireless communications, and home entertainment.

The new OVP Fast Processor Model uses Imperas’ high performance code morphing technology to allow software engineers to execute PowerPC development code at hundreds of million lines per second on their desktop personal computers. Incorporated within the model is Imperas’ range of advanced development tools for efficient software analysis and debug.

Imperas exhibit and demonstrate OVP at Embedded Technology show 2013, Nov 20-22, Yokohama, Japan

Embedded Technology 2013 ( http://www.embeddedtech.net/), November 20-22 in Yokohama, Japan, is the world’s largest  trade show and conference for embedded system designers and  managers.  The ET Conference & Exhibition introduces advanced technologies and solutions for emerging embedded applications, including digital consumer electronics,  automotive, wireless/ubiquitous computing and factory automation.

Imperas will again this year have a booth in the Venture Village area of the exhibit hall.  Imperas will demonstrate both OVP and Imperas tools, showing how virtual platform based technologies can provide benefits such as earlier software development (pre-silicon), and improved software testing (post-silicon).

Altera discuss successful use of Imperas tools to find complex OS bugs

At the June 3, 2013 North American SystemC User Group meeting as part of the Design Automation Conference 2013 in Austin Texas, Victoria (Vicki) Mitchell of Altera presented a paper titled: Embedded Software Dynamic Analysis: A New Life for the Virtual Platform.

The presentation introduces the Software part of HW/SW co-design, with the issues of Code Safety and Security being addressed and how Dynamic Analysis using simulation and virtual platforms can address them. It continues with Software Analysis by using a platform modeled with OVP and using the Imperas tools shows examples of how bugs were found in the use of Linux and uC/OS-ii. The presentation concludes with the conclusion that the use of virtual platforms and dynamic analysis provides safe and secure code for embedded systems.

The slides are available here:  http://nascug.org/events/19th/Dynamic_Analysis_6-3-2013.pdf

Verification blogger reviews DAC presentation

At the recent DAC in Jun 2013 in Austin Texas, Vicki Mitchell of Altera presented about the use of Imperas tools to find bugs in Operating Systems and RTOS. Ther is more information here.

Miyashita-san of Fuji Xerox follows developments regarding OVP and Imperas and gives an update in his blog here: http://blogs.yahoo.co.jp/verification_engineer/68146679.html

 

 

 

Imperas and OVP to be demonstrated at ARM TechCon 2013, Oct 29-31, Silicon Valley

ARM Techcon 2013 ( http://www.armtechcon.com/), October 29-31 in Santa Clara, California, is the largest conference devoted to developers of ARM-based SoCs, software and systems, bringing together users, hardware and software vendors, ARM technologists and others in the ARM ecosystem.

Imperas at ARM Techcon:  Simon Davidmann will be participating on a panel session, and Imperas will have a booth in the exhibits. 

Panel title:  The Future of Collaborative Embedded SW Development, from the viewpoint of one Technology Chain Gang

Panel abstract:  The creation of a modern embedded processor platform solution requires components from a “technology chain” of contributing companies, including processor, platform, OS, IP, and tool providers.  The multicore architecture of these platforms, as well as the use of advanced processor features like TrustZone and virtualization, places a heavy demand on associated software development, requiring the entire technology chain to derive the most effective solution together.  Come hear these key members of one particular technology chain discuss their collaboration and the resulting evolution of next generation embedded software development methodologies.

Nikkei Electronics article about Imperas new products

Imperas recently announced its new generation of Software Development Tools that utilize Virtual Platforms.

Nikkei Electronics in Japan have written an article in Japanese about this announcement - to read the article please follow this link: http://techon.nikkeibp.co.jp/article/NEWS/20130822/298823/

 

Pages