All Imperas News

Imperas Paper at TVS DVClub 2016 Software Verification for Low Power Safety Critical Systems

<b>Abstract</b>:
<p>In November 2016, Simon Davidmann of Imperas gave a talk on how Imperas technology is being used for Timing Analysis, Power Analysis and Fault Simulation
to assist with Software Verification. Here are the slides. The talk was split into two sections.</p>
<p>The first section covers software verification for embedded systems and provides an overview of the challenges of many processors
in current embedded systems. It leads into the requirements for software verification and introduces specific embedded software development issues. It then
explains using simulation / virtual platforms and advanced tools to make embedded software development easier, quicker, and more affordable.</p>
<p>There are explanations of how simulation can be used with continuous integration and other modern software development practices.</p>
<p>The second section of the talk introduces the issues related to low power and how to use simulation to get a handle on the affects of software on low power design.
</p>
<p>Imperas is collaborating with several institutes and universities around the world and these collaborations are explored.</p>
<p>The use of Imperas Instruction Accurate simulation used for Timing Analysis, Power Analysis and Fault Simulation are discussed with examples and case studies.</p>

Fast Processor Model of Renesas RL78 CPU Released by Imperas for Open Virtual Platforms

eSOL TRINITY, Imperas Partner, Developed the RL78 Model

Oxford, United Kingdom, May 31, 2016 - Imperas™ and eSOL TRINITY announced today the release of the Open Virtual Platforms™ (OVP™) Fast Processor Model for the Renesas RL78 CPU.  Example virtual platforms have also been released, as well as support for the new model in the Imperas M*SDK™ advanced software development tools.  The model of the RL78 was developed by eSOL TRINITY, Imperas’ partner in Japan, providing technical support for Imperas customers as well as services for embedded software development. 

The processor core model and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/Renesas.  The model of the RL78 processor core, as well as models of other Renesas processors, work with the Imperas and OVP simulators, including the QuantumLeap™ parallel simulation accelerator, and have shown exceptionally fast performance of hundreds of millions of instructions per second. 

ARM Cortex-A72 Models and Virtual Platforms Released by Imperas and Open Virtual Platforms

ARMv8 Support From Imperas Accelerates Embedded Software Development

Oxford, United Kingdom, May 24, 2016 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, announced the availability of models and virtual platforms for the Cortex-A72 ARMv8 processors, in addition to the previously released Cortex-A53 and A57 models.  This boosts the Imperas Open Virtual Platforms™ (OVP™) processor model library to over 160 models across a spectrum of IP vendors.  Over 40 ARM cores are supported including Cortex-A, Cortex-R and Cortex-M families.

Imperas support for ARMv8 cores, such as the Cortex-A72, includes models, Extendable Platform Kits™ (EPKs™), integration with ARM DS-5 for software debug and Linaro Linux booting on the virtual platforms.

Imperas Cortex-A72 ARM processor models are available in single-core, multi-core and multi-cluster configurations enabling high performance simulations of platforms ranging from simple single cores all the way to many core systems. Imperas has also built a model of the ARM GICv3 interrupt controller, which is available with the processor core models.

prpl Security Group & Imperas Address IoT Security Challenges via Multi-Domain Virtualization

As a member of the prpl Foundation and its security working group, Imperas is working with several member who are using OVP technologies to develop and explore the use of hypervisors to improve device security, amongst other things.

In this article on EBN online, concern over automotive security is discussed and a hypervisor from SELTECH is introduced.

car hijacked using security breach

As a founding member of the Security Working Group of the prpl Foundation, Imperas is supporting the definition of a new open security framework for deploying secured and authenticated virtualized services in the Internet of Things (IoT) and related emerging markets.

Recent news shows that security is a key challenge to the wide scope and deployment of IoT, with varied consequences across many IoT markets. Imagine automotive hijacking. Power grid failure. Financial security breaches. Health care hacking. Consequences are severe: successful security measures in the IoT ecosystem will...

To read the full article click here.

To visit prpl click here.

Imperas Virtual Platform Based Software Tools at DAC and Embedded TechCon 2016

Linux Tutorial, Presentations on OS Porting and Software Development for ARM and Demos

OXFORD, United Kingdom, May 16, 2016 -- Imperas Software Ltd., the leader in high-performance software simulation, today announced their participation at the Design Automation Conference (DAC) 2016, inviting developers of electronic products to register for a demonstration of Imperas virtual platforms for embedded software and systems development, debug and test at the Imperas booth #839. Attendees can also register for the tutorial on Linux porting and bring up, delivered by Imperas. 

At the co-located Embedded TechCon conference, Imperas will be presenting papers on OS and driver development, and on the use of virtual platforms for software development targeted at ARM-based devices.

Automating System Design

The impact of the chip’s changing role in the system is becoming clearer.

Ann Steffora Mutschler of Semiconductor Engineering has written an interesting article on System Level design and its automation.

There are comments from Wally Rhines (chairman & CEO of Mentor), Simon Davidmann (president & CEO Imperas), Nandan Nayampally (VP marketing ARM), Nimish Modi (snr VP Cadence) and John Koeter (VP Synopsys).

Change is underway in the chip design world, creating opportunities and challenges that reach far beyond questions about whether Moore’s Law is slowing or stopping.

Never before in the history of semiconductors has design been so complex and sophisticated, and never has it touched so many lives in so many interesting ways. This is...

To read the article, click here.

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ESL Flow Is Dead

Brian Bailey of Semiconductor Engineering recently chaired a panel at DVCon on ESL.

Expecting the future to replicate the past always leads to surprises and when it comes to migration of abstraction for semiconductor design, the future remains unclear.

Brian interviewed several industry leaders with experience in the field and provides interesting insights into why ESL took a long time to get where it has...

Simon Davidmann, CEO of Imperas was quoted several times. For example Simon said: “Everyone is trying to do more with RTL, more design, more verification, more complexity, and they needed a better solution. The industry came up with a C++ class language (SystemC) and then tried to look at what they could do with it. What is needed is to move away from the EDA vendors trying to define ways to sell the technologies they have, to asking the question, ‘How are we going to design systems which are incredibly complex, containing many processors, many hardware blocks and more software than you can imagine?’ How can we design things in a better way? How do we verify things in a better way?”...

To read the article, click here.

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