All Imperas News

prpl Security Group & Imperas Address IoT Security Challenges via Multi-Domain Virtualization

As a member of the prpl Foundation and its security working group, Imperas is working with several member who are using OVP technologies to develop and explore the use of hypervisors to improve device security, amongst other things.

In this article on EBN online, concern over automotive security is discussed and a hypervisor from SELTECH is introduced.

car hijacked using security breach

As a founding member of the Security Working Group of the prpl Foundation, Imperas is supporting the definition of a new open security framework for deploying secured and authenticated virtualized services in the Internet of Things (IoT) and related emerging markets.

Recent news shows that security is a key challenge to the wide scope and deployment of IoT, with varied consequences across many IoT markets. Imagine automotive hijacking. Power grid failure. Financial security breaches. Health care hacking. Consequences are severe: successful security measures in the IoT ecosystem will...

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Imperas Virtual Platform Based Software Tools at DAC and Embedded TechCon 2016

Linux Tutorial, Presentations on OS Porting and Software Development for ARM and Demos

OXFORD, United Kingdom, May 16, 2016 -- Imperas Software Ltd., the leader in high-performance software simulation, today announced their participation at the Design Automation Conference (DAC) 2016, inviting developers of electronic products to register for a demonstration of Imperas virtual platforms for embedded software and systems development, debug and test at the Imperas booth #839. Attendees can also register for the tutorial on Linux porting and bring up, delivered by Imperas. 

At the co-located Embedded TechCon conference, Imperas will be presenting papers on OS and driver development, and on the use of virtual platforms for software development targeted at ARM-based devices.

Automating System Design

The impact of the chip’s changing role in the system is becoming clearer.

Ann Steffora Mutschler of Semiconductor Engineering has written an interesting article on System Level design and its automation.

There are comments from Wally Rhines (chairman & CEO of Mentor), Simon Davidmann (president & CEO Imperas), Nandan Nayampally (VP marketing ARM), Nimish Modi (snr VP Cadence) and John Koeter (VP Synopsys).

Change is underway in the chip design world, creating opportunities and challenges that reach far beyond questions about whether Moore’s Law is slowing or stopping.

Never before in the history of semiconductors has design been so complex and sophisticated, and never has it touched so many lives in so many interesting ways. This is...

To read the article, click here.

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ESL Flow Is Dead

Brian Bailey of Semiconductor Engineering recently chaired a panel at DVCon on ESL.

Expecting the future to replicate the past always leads to surprises and when it comes to migration of abstraction for semiconductor design, the future remains unclear.

Brian interviewed several industry leaders with experience in the field and provides interesting insights into why ESL took a long time to get where it has...

Simon Davidmann, CEO of Imperas was quoted several times. For example Simon said: “Everyone is trying to do more with RTL, more design, more verification, more complexity, and they needed a better solution. The industry came up with a C++ class language (SystemC) and then tried to look at what they could do with it. What is needed is to move away from the EDA vendors trying to define ways to sell the technologies they have, to asking the question, ‘How are we going to design systems which are incredibly complex, containing many processors, many hardware blocks and more software than you can imagine?’ How can we design things in a better way? How do we verify things in a better way?”...

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System-Level Verification Tackles New Role

Brian Bailey of Semiconductor Engineering recently got several experts together for a round table discussion entitled:

The role of system-level verification is not the same as block-level verification and requires different ways to think about the problem.

The experts included Larry Lapides of Imperas, and also staff from Cadence, Mentor, and Breker Verification.

The discussion started with reflection on a keynote at DVCon this year that Wally Rhines, chairman and CEO of Mentor Graphics, gave. He said that if you pull together a bunch of pre-verified IP blocks, it does not change the verification problem at the system level. That sounds like a problem...

Follow the link to read the first episode / article click here.

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prpl Foundation Publish First Newsletter

The prpl Foundation recently published its first newsletter, as a way of extending communications with the embedded systems community. 

Imperas CEO and Open Virtual Platforms™ (OVP™) founder Simon Davidmann wrote an article for the newsletter, titled “prpl Security Group and Imperas Address IoT Security Challenges via Multi-Domain Virtualization.”  That’s quite the long title.  What was Simon saying?

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“Redefining ESL” Panel Insights from DVCon 2016

At the recent DVCon 2016 conference in Silicon Valley, there was a lively and popular panel, with 135 attending despite the early hour.  Moderated by Brian Bailey of Semiconductor Engineering, it featured a variety of views on the role of ESL (“Electronic System Level”) in design and verification for both hardware and software.

Panelists included (from left to right below)

Patrick Sheridan, Synopsys
Raik Brinkmann, One Spin
Simon Davidmann, Imperas Software Ltd.
Bryan Bowyer, Mentor
Dave Pursley, Cadence
Adnan Hamid, Breker

Simon Davidmann of Imperas Software Ltd. kicked off the discussion by questioning the very definition of ESL, calling the terminology a “misnomer” and contending that the key issue is designing electronic products: not just the hardware, but both hardware and software. He stated: “EDA vendors need to..."

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Imperas CEO Simon Davidmann Speaks at DATE 2016 in Germany

DATE 2016 Tutorial: Virtual Platforms in the Internet of Things (IoT) Era

OXFORD, United Kingdom, February 16, 2016 -- Imperas Software Ltd., leader in high-performance software simulation and virtual prototyping, today announced that CEO Simon Davidmann will give a tutorial at DATE (Design, Automation & Test in Europe) 2016. DATE is a leading international event for design and engineering of systems-on-chip, systems-on-board and embedded systems software. Imperas CEO Simon Davidmann will provide an introduction to virtual platforms, speaking on embedded software development, debugging, analysis, and verification with virtual platforms supporting today's multiprocessor SoCs, as part of the tutorial “Internet-of-Things: Virtual Platforms in the Internet-of-Things Era – State of the art and perspectives.” 

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