Presentation on Imperas RISC-V models and simulation for software developers from University of California SoC Conference 2017


Imperas presented a paper titled "RISC-V Models and Simulation Enable Early Software Bring Up" at the 2017 University of California SoC Conference. The paper first discusses the likely areas where RISC-V will be used, including IoT applications, and as a helper or "minion" processor on larger SoCs doing tasks like power or communications management. The success of RISC-V in the short term in these areas, as well as longer term in these and other areas, will be dependent upon the strength, the breadth and the depth, of the RISC-V software ecosystem. Because while RISC-V may have some technical and business advantages over other processor cores, the switching costs of moving to RISC-V need to be minimized, and those switching costs are more in the software than the hardware.

The paper continues and discusses virtual platform technology, and the use of virtual platforms for early software porting and bring up and for more comprehensive software testing.  The status of RISC-V models from Imperas and Open Virtual Platforms (OVP) was elaborated: 

  • Processor models
    • Generic RISC-V models
      • RV32IMAC
      • RV64IMAC
    • SiFive
      • E31
      • E51
    • Andes
      • N25
      • NX25
  • Extendable Platform Kits (EPKs)
    • Microsemi SmartFusion2 RISC-V FreeRTOS EPK
    • Andes FreeRTOS EPK
    • Andes – Linux Heterogeneous EPK

Here are the slides presented.