RISC-V Custom Instruction Design and Verification Flow

This demonstration video covers the complete software design flow to add custom instructions to a RISC-V processor model. Covering the key stages of identifying opportunities for custom instructions, through profiling new instructions to final testing and documentation. The complete flow is illustrated with an example based on custom instructions for optimizing the well-known ChaCha20 encryption algorithm for security applications.The example files are available for download from www.ovpworld.org/riscv.Additional information on RISC-V models and tools can be found at www.imperas.com/riscv.