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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

RISC-V Custom Instruction Design and Verification Flow

This demonstration video covers the complete software design flow to add custom instructions to a RISC-V processor model. Covering the key stages of identifying opportunities for custom instructions, through profiling new instructions to final testing and documentation. The complete flow is illustrated with an example based on custom instructions for optimizing the well-known ChaCha20 encryption algorithm for security applications.The example files are available for download from www.ovpworld.org/riscv.Additional information on RISC-V models and tools can be found at www.imperas.com/riscv.

Comments

  • Miroslav Popovic

    Professor, University of Novi Sad, Serbia

    Using Imperas and OVP in my course on Real-Time System Programming is an immense benefit. Embedded software development is a growing need worldwide, and advanced methodologies such as Imperas delivers are required for accelerated coding and quality.

  • Alexander Redkin, CEO

    Syntacore

    As one of the first IP providers for RISC-V cores, we see the importance of compliance as the RISC-V ecosystem develops. riscvOVPsim is a solid starting point for developers looking for a RISC V ISS (Instruction Set Simulator) for test and verification.