RISC-V Custom Instruction Flow Application Note

A RISC-V processor has several defined decode spaces, for example custom0, custom1 etc. into which new custom instructions can be added. OVP Fast processor models can be extended without modification to the pre-compiled and verified base processor model source code using one or more extension libraries. An extension library can be loaded as part of a virtual platform definition in addition to the base processor model and can provide decode and implementation of behavior for the instructions as well as additional registers.

Including more timing information for the instruction execution provides a cycle approximate simulation. This provides a better approximation to the time of the execution of an application on the actual hardware. The additional timing information is loaded into the virtual platform as an extension library so there is no change to the functional behavior provided by the processor model.

This application goes through the complete flow of functional validation of the application, extension of the processor with custom instructions, analysis of the application execution and optimization of the custom instruction implementation and its documentation.