Zbyszek Zalewski, General Manager, Hardware Division
Aldec
The integration of HES with OVPsim enables hardware and software design teams to implement virtual models of processors, memory and peripherals while the RTL modules run in the emulator board. This new integration provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.
Shubhodeep Roy Choudhury, co-founder and Managing Director
Valtrix Systems
Test and verification of RISC-V open ISA cores is the most demanding challenge for processor developers today. By partnering with Imperas and using the OVP virtual library of platforms we can offer customers a complete solution across all aspects of RISC-V processor verification, test and compliance.