The open RISC-V ISA specification is an excellent starting point and open-source processor IP cores, such as the CORE-V family, have real potential to change the industry.
The high-quality open-source CORE-V CV32E40P core now allows the broadest participation in the RISC-V revolution, the OpenHW MCU Dev/Kit project is just one example of the innovations that can now be developed from the quality foundation provided by the CV32E40P core, having been verified with the CORE-V-VERIF testbench which leverages the Imperas RISC-V golden reference model.
Stephan Werner
Karlsruhe Institute of Technology
M*SDK, the OVP APIs and the OVP library of models have been a great asset to the FlexTiles project, enabling us to quickly create a virtual platform for our advanced architecture. We were able to use the Imperas technology and tools to develop multiple demonstrations of the FlexTiles architecture, including multiple hardware configurations, the Network on Chip (NoC) developed in this project and the operating system and software tools for FlexTiles.