The pace of innovation in markets such as the latest 5G communication networks and infrastructure offers many opportunities for new domain-specific SoC solutions.
As a leading supplier of silicon IP, we fully appreciate the role of the ecosystem in supporting our lead customers in delivering new devices to market. We are pleased Imperas have now released the first Catapult RISC-V CPU Imperas reference model for the IMG RTXM-2200, which provides our mutual customers a proven path to accelerate projects to market.
Dr. Charlie Su, President and CTO
Andes Technology Corp.
RISC-V represents the potential for innovation, and it is the implementation of great ideas that are really generating exceptional results.
To unlock such potentials, Andes provides the AndeSysC™ environment, an extensible and near-cycle accurate SystemC model library for all AndesCore®. SoC architects can use it to construct a SystemC based virtual platform for performance evaluation of critical code segment and hardware/software co-optimization. ACE technology helps users implement custom functions and instructions, and it directly connects to the AndeSysC™ environment. Now with the close integration with the Imperas fast reference models and tools, design teams can embark on architecture exploration with complete application software for the next generation of domain specific devices with a seamless path to ACE implementation.