ARMv8 Support From Imperas Accelerates Embedded Software Development
Oxford, United Kingdom, May 24, 2016 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, announced the availability of models and virtual platforms for the Cortex-A72 ARMv8 processors, in addition to the previously released Cortex-A53 and A57 models. This boosts the Imperas Open Virtual Platforms™ (OVP™) processor model library to over 160 models across a spectrum of IP vendors. Over 40 ARM cores are supported including Cortex-A, Cortex-R and Cortex-M families.
Imperas support for ARMv8 cores, such as the Cortex-A72, includes models, Extendable Platform Kits™ (EPKs™), integration with ARM DS-5 for software debug and Linaro Linux booting on the virtual platforms.
Imperas Cortex-A72 ARM processor models are available in single-core, multi-core and multi-cluster configurations enabling high performance simulations of platforms ranging from simple single cores all the way to many core systems. Imperas has also built a model of the ARM GICv3 interrupt controller, which is available with the processor core models.
Extendable Platform Kits for ARMv8 processor cores running Linux are also available. EPKs are virtual platforms (simulation models) of the target devices, including the processor model(s) plus peripheral models sufficient to boot an operating system or run bare metal applications. These EPKs, available for download from the OVP website, allow users to run high-speed simulations of ARM-based SoCs and platforms on any suitable PC. EPKs provide a base for users to extend and customize the functionality of the virtual platform, to closer reflect their own platform, by adding more component models, running different operating systems or adding additional applications. The platform and the peripheral models included in the EPKs are open source, so that users can easily add new models to the platform as well as modify the existing models.
These models and EPKs are part of the complete Imperas virtual platform environment for embedded software and hardware development and verification solutions.
Models of the ARM processor cores, as well as models of other processors, work with the Imperas and OVP simulators, and have shown exceptionally fast performance of hundreds of millions of instructions per second. With the Imperas QuantumLeap™ parallel simulation accelerator, additional speed can be achieved for virtual platforms which include multiple processor instances, multicore processors and processors that support hardware multi-threading. This add-on to the Imperas simulator provides MPonMP™ (MultiProcessor target on MultiProcessor host) technology to take advantage of the multiple x86 cores in the host machine. This can result, for example, in an increase in performance of 2.25x for a 4-core virtual platform with SMP architecture running on a 4-core host PC.
OVP models also work with the Imperas advanced tools for multicore software development, verification, analysis and debug, including M*SDK™ advanced software development solutions and key tools for hardware-dependent software development such as OS and CPU-aware tracing (instruction, function, task, event), profiling, code coverage and memory analysis. The tools utilize the Imperas SlipStreamer™ patent-pending binary interception technology. SlipStreamer enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.
“This release is just the latest in our line of ARMv8 processor models and EPKs, leveraging our advanced virtual platform technology. With these models and platforms, users can benefit from high performance simulation and embedded software development and test tools,” said Simon Davidmann, president and CEO of Imperas.
For the latest list of ARM processor support, please see www.OVPworld.org.
For more information about Imperas, please see www.imperas.com.
All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.
# # #