Imperas in the News

New MIPS I7200 Processor Core Delivers Unmatched Performance and Efficiency For Advanced LTE/5G Communications And Networking IC Designs

MIPS

Highly efficient parallel processing, fast response to real-time events, and 50% performance gains position the I7200 as the core of choice for high performance embedded applications

Santa Clara, Calif. – May 1st, 2018  MIPS, provider of the widely used MIPS processor architecture and IP cores for licensing, today announced the I7200 multi-threaded multi-core processor, a new high performance licensable IP core in their midrange 32-bit product lineup. Class-leading efficiency is essential to power sensitive applications such as the high bandwidth modem subsystems in Advanced LTE Pro and upcoming 5G smartphone SoCs, as well as networking ICs, and other applications. The I7200 delivers 50% higher performance in less than 20% area increase than the previous generation from MIPS.

Imperas and Andes Extend Partnership, Delivering Models and Virtual Platforms for Andes RISC-V Cores with New AndeStar V5m Extensions

Ashling Systems

AndeStar V5m Extensions for AndesCore N25 and NX25 Processors Now Supported by Imperas Virtual Platform Software Solutions and Models

Oxford, United Kingdom, May 1, 2018 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, and Andes Technology Corporation, today announced Open Virtual Platforms™ (OVP™) models and virtual platform support for powerful new extensions in the AndesCore™ N25 and NX25 IP processors, which are AndeStar™ V5 32-bit and 64-bit architectures based on the RISC-V technologies.

Building on the Imperas and Andes partnership to support Andes’ RISC-V cores announced in November 2017, the new Imperas reference models support the Andes AndeStar™ V5m extensions.

Imperas is the leading provider of RISC-V processor models and virtual prototype solutions, including both of the Andes N25 32-bit and NX25 64-bit cores. The new Andes models, with extensions, are available now from Imperas and the Open Virtual Platforms (OVP) website.

Virtual platform for RISC-V: Zero to Linux in 5 seconds or less

 

Imperas Software, Ltd. formed part of the growing ecosystem of support for RISC-V, together with six other members, at the RISC-V Foundation booth at embedded world in Nuremberg, February- March 2018. Imperas featured a demo of the RISC-V virtual platform, showcasing both FreeRTOS and Linux booting.

Imperas at 7th RISC-V workshop

Imperas presented two papers and took part in the exhibition. To read the article by Kevin McDermott in Embedded Computing Design, click here.

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Ashling and Imperas Partner to Extend the RISC-V Ecosystem

Ashling Systems

RISC-V Community Gets a Turnkey Software Solution Via Ashling/ Imperas Alliance

Embedded World 2018, Nuremburg, Germany–February 26, 2018Ashling Systems (a subsidiary of the NeST Group) and Imperas Software today announced a partnership to provide integrated tools and solutions for RISC-V software development. The technology aspects of this alliance include the integration of Imperas’ high-performance virtual platforms, simulation engines and models into Ashling’s own RiscFree™ IDE and tools offering. On the business side, Ashling will promote, sell and support this new, comprehensive, turnkey solution spanning the solutions of both companies.

As leaders in the RISC-V initiative, both companies believe that the market demands an expanded ecosystem, a turnkey solution, and one-stop shopping for RISC-V development tools. Ashling is taking the lead in promoting and selling its RiscFree™ IDE integrated solution for RISC-V software development, debug and modeling.

Magillem Partners with Imperas

Magillem

A winning combination in delivering value to system developers

Paris, France - February 26th, 2018 - Since 2015, Magillem (www.magillem.com), the leading provider  of  front-end  design  xml  solutions  and  best-in-class  tools  to  reduce  the  global  cost  of
complex  designs,  has  partnered  with  Imperas  (www.imperas.com),  which  is  revolutionizing embedded  software development,  debug and  test  for multi-core  designs  via  high-performance
virtual  platforms,  high-level  software  and  system  simulation,  and  open  models.  Together, Magillem and Imperas provide a unique virtual prototyping solution set, fully based on the IEEE standards IP-XACT and SystemC. 

11 Myths About the RISC-V ISA

Semiconductor Engineering

Despite its rich ecosystem and growing number of real-world implementations, misconceptions about RISC-V are keeping companies around the world from fully realizing its benefits.

Ted Marena of Microsemi has written an interesting article in Electronic Design about the RISC-V ecosystem.

Many companies today are exploring free, open-source hardware and software as an alternative to closed, costly instruction set architectures (ISAs).

RISC-V is a free, open, and extensible ISA that’s redefining the flexibility, scalability, extensibility, and modularity of chip designs.

RISC-V.org

Despite its rich ecosystem and growing number of real-world implementations, there are misconceptions about RISC-V that have companies holding back from fully realizing its benefits.

To read the full article and see the 11 myths..., click here.

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Microsemi and Imperas Announce Extendable Platform Kit for Microsemi Mi-V RISC-V Soft CPUs

Microsemi Corporation

Collaboration Enabled by Microsemi's Mi-V Ecosystem, Designed to Drive Adoption of FPGA-Based RISC-V Designs

Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, and Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced the Extendable Platform Kit™ for Microsemi Mi-V™ RISC-V soft central processing units (CPUs). The collaboration delivers the first commercially available instruction set simulator (ISS) for Microsemi's Mi-V ecosystem, a program designed to increase adoption of Microsemi's RISC-V soft CPU product family utilizing RISC-V open instruction set architectures (ISAs).

To read the Microsemi press release, click here.

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Inflection point for RISC-V. The 7th RISC-V workshop in Silicon Valley

Embedded Computing Design

Inflection point for RISC-V: The 7th RISC-V workshop in Silicon Valley

Imperas participated in the 7th RISC-V workshop in Milpitas, California, with a talk and demonstrations. 

Imperas at 7th RISC-V workshop

Each workshop has a different feel to it, and this one seems to be the inflection point in RISC-V maturity. Whereas past workshops felt a bit like a revival tent meeting, with most everyone caught up in the religion of RISC-V, at this workshop there was also a strong...

To read the article in Embedded Computing Design, click here.

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Andes partners with EDA tool vendors for more RISC-V SoC support

Andes Technology

Andes partners with EDA tool vendors for more RISC-V SoC support

Andes Technology announces its partnership with several tools vendors including Imperas, Lauterbach, Mentor, a Siemens Business, and UltraSoC to bring their system-on-chip (SoC) development environments to Andes V5 processors and the RISC-V community.

To read the Andes press release, click here.

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How To Handle Concurrency

Semiconductor Engineering

How To Handle Concurrency.

The recent article in Semiconductor Engineering by Brian Bailey on Handling Concurrency, includes discussion from Simon Davidmann of Imperas.

System complexity is skyrocketing. The evolution of processing architectures has solved many problems within a chip, but for each problem solved another one was created. Concurrency is one of those issues, and it has been getting much more attention lately.

To read the article, click here.

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