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NSITEXE’s RISC-V Success Using ImperasDV and Cadence

To address the challenge of design verification for the Akaria products, NSITEXE turned to RISC-V solutions from Imperas Software and Cadence. The ImperasDV RISC-V processor verification solution, combined with the Xcelium RTL simulation and debug solution from Cadence, were instrumental in achieving first-time silicon success.

For more information, please email Imperas at info@imperas.com

Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Comments

  • Nobuyuki Ueyama, President

    eSOL TRINITY Co., Ltd.

    The open ISA of RISC-V is enabling a new wave of processor design innovation across the spectrum of compute requirements in almost all market segments.

    High quality processor verification is not a simple task, but the ease of use and configurable approach with RVVI offered by ImperasDV enables the eSOL TRINITY team to support the expert design teams at NSITEXE and other leading adopters of RISC-V in Japan.

  • Enno Wein, Founder and CEO

    ProximusDA

    OVP Fast Processor Models are an essential foundation to system level design, helping to unleash innovation in this area. By providing free models and associated virtual prototyping infrastructure, OVP enables the ecosystem to focus on advanced technologies and solutions.